In the recent global semiconductor boom, Europe also doesn't want to miss it.
According to the European Chip Act they passed in September last year, the EU hopes to strengthen local manufacturing activities, stimulate the European design ecosystem, and support the expansion and innovation of the entire value chain. Specifically, the EU's chip bill has three pillars:
One is the European chip program, which aims to promote the transfer of knowledge from laboratories to factories, narrow the gap between research and innovation and industrial activities, and promote European companies to industrialize innovative technologies, strengthening Europe's technological leadership position. The European Chip Program will mainly be implemented by the Chip Consortium. The plan will receive support from the EU with 3.3 billion euros in funding, and it is expected that member states will also provide matching funds.
The second is to incentivize public and private investment in the manufacturing facilities of chip manufacturers and their suppliers. The approach is to ensure supply security by attracting investment and improving the production capacity of semiconductor manufacturing.
Thirdly, establish a coordination mechanism between member states and the committee to strengthen cooperation among member states, monitor semiconductor supply, estimate demand, predict shortages, and initiate crisis phases when necessary;
According to the EU's chip plan, they hope to double their global market share to 20% by 2030. From the current perspective, although there has been occasional progress in European chips, this is not an easy goal to achieve.
7nm FD SOI takes an important step forward
As transistors transitioned from flat to 3D, there was once a competition between FinFET and FD SOI, but with strong support from Intel and TSMC, FinFET ultimately emerged victorious. But Europe has recently set a relatively aggressive goal in FD SOI and taken an important step.
Last week, France announced the launch of a € 830 million 10nm and 7nm FDSOI technology trial production line for the design of next-generation 5G and 6G chips and systems. This FAMES semiconductor experimental production line located in Grenoble, France has five key areas, from materials to packaging. The cost will reach up to 830 million euros, with the ultimate goal of building the next generation stacked 3D RF system equipment for 5G and 6G.
It is reported that the production line will develop the next generation of fully depleted silicon on insulator (FD SOI) process technology for foundries such as GlobalFoundries and Samsung, as well as chip manufacturers such as Qualcomm and STMicroelectronics, with nodes up to 10nm and 7nm.
"The key markets are 5G and 6G, and in 6G, we need new filters ranging from 7 GHz to 15 GHz, which is very promising and requires new chips because there will be over 100 filters to be combined and placed on top of FDSOI transistors," said Jean Ren é L è quepeys, Chief Technology Officer of CEA Leti.
He stated that the 10nm FD SOI process will have a high frequency (Ft) of 450GHz, while the 7nm process is expected to reach 540GHz.
He said, "For pure digital applications, it will have the same performance as 5nm FinFET, but for RF and analog applications, it will have better performance." Its polysilicon spacing is 64nm, and the metal spacing is 48nm and 40nm.
He said, "In the future, we need to add non-volatile memory with different functions for a wide range of applications."
For SoC, adopting a single-chip solution is not a good solution because we need to choose the right technology for the right functionality. To achieve this, we need heterogeneous integration, stacking chips with 3D heterogeneity and 3D single-chip.
"There are also limitations in terms of power, so we need DC-DC converters with miniature inductors. The first step will be to separate them, but they can be integrated. These can all be mixed together to create disruptive chip architectures," he said.
It's just about 5G and 6G wireless. FDSOI with adaptive back bias is also a key low-power technology for quantum processors, and Leti is researching several different quantum technologies, including photonics.
"We have a lot of bets, including quantum, which is a very important part for us, but we support other French and European startups exploring superconducting qubits and photonics. This is clearly a major ambition to become one of the first companies to find the right solutions to scale up and industrialize, as it will bring differences," said Leti CEO S é bastien Dauv é.
Leti is developing CryoCMOS technology to control circuits with ECC error code correction capabilities. "We need a package specifically designed to work at low temperatures, which is also a major issue. CEA is researching a method of using full stack programming for a new computing engine," said Chief Technology Officer L è quepeys.
In order to produce this production line, Leti is expanding its factory by adding two clean rooms and equipment, including an EUV lithography system, partially to accommodate the FAMES experimental production line. This will be a virtual experimental production line with equipment distributed across multiple cleanrooms in the factory, which will also be used for other projects.
The data shows that they installed an ASML 300mm Twinscan 2050i immersion lithography machine in December last year, and part of the FAMES project will determine whether this equipment can be used for processes with line widths as low as 7nm in the FD SOI process. It is expected that the EUV lithography scanner will not be installed until 2026.
"The research and development work will end in 2028, but it will still be open until 2031- the first batch of contracts will open from April 2025 to September 2025, and they can develop their own IP. We will keep the IP of this technology, but for the final IC design, our partners will have their own IP. This is a big deal," L è quepeys said.
FAMES is one of the four experimental production lines in Europe, and its development has been coordinated to ensure that there will be no significant competition or overlap. In terms of technology focus, in addition to FD SOI ranging from 10nm to 7nm, this production line also focuses on embedded non-volatile memory and small inductors, as well as DC-DC converters for power management integrated circuits (PMICs).
Wafer factories frequently encounter setbacks
Building a self owned wafer factory ecosystem is a crucial part of the EU's chip program. In order to achieve this goal, they also attracted TSMC and Intel to build factories or expand production locally. But according to the latest news, delays seem to have become the norm.
Firstly, in August 2023, TSMC, Robert Bosch GmbH, Infineon Technologies, and NXP Semiconductor announced plans to jointly invest in the construction of the European Semiconductor Manufacturing Company (ESMC) GmbH in Dresden, Germany, to provide advanced semiconductor manufacturing services.
The press release stated that the project is planned according to the framework of the European Chip Act, with an expected monthly production capacity of 40000 300 millimeter (12 inch) wafers, using TSMC's 28/22 nanometer planar CMOS and 16/12 nanometer FinFET process technology.
At a seminar held in the Netherlands in May, Paul de Bot, President of TSMC Europe, confirmed that the project is expected to start construction in the fourth quarter of this year and is expected to start production in 2027. But considering the setbacks TSMC has encountered in the United States, we reserve our opinion on whether this progress can proceed as scheduled. Silicon Saxony consultant Torsten Thieme also stated that the German labor union has always taken a tough stance on employers, which is one of the challenges TSMC must overcome.
Thieme stated that in the face of labor shortages, TSMC needs to provide competitive compensation to attract production line workers and engineers to work for ESMC.
This is a dilemma for a wafer fab.
Take another look at Intel, which is expanding production in Europe. Recently, it has been reported that due to EU subsidies, they will slow down the construction progress of the 1nm factory in Europe.
According to the global media Volkstimme, the construction of Intel's Fab 29.1 and Fab 29.2 factories near Magdeburg, Germany has been delayed due to waiting for EU subsidy approval and the need to remove and reuse black soil. The start date has been postponed from the summer of 2024 to May 2025.
Earlier reports showed that the chip factory was initially expected to start construction in 1H23, but due to delayed subsidies, construction was postponed until the summer of 2024. Moreover, the topsoil on the construction site will not be cleared until May 2025 at the earliest.
It is reported that Intel Fab 29.1 and Fab 29.2 were originally planned to be put into operation by the end of 2027 and are expected to adopt advanced manufacturing processes, which may be nodes of Intel 14A (1.4nm) and Intel 10A (1nm) processes. However, Intel now estimates that the construction of these two factories will take four to five years and is expected to begin production between 2029 and 2030.
The other factory that was delayed due to subsidies is WolfSpeedd.
The report points out that SiC giant Wolfspeed has postponed plans to build a $3 billion factory in Germany, highlighting the difficulties faced by the European Union in increasing semiconductor production and reducing dependence on Asian chips.
A spokesperson stated that the factory planned to be established in Saarland will produce computer chips for electric vehicles, which has not been completely cancelled and the company is still seeking funding. But the spokesperson added that due to the weak electric vehicle markets in Europe and the United States, Wolfspeed, headquartered in North Carolina, has reduced capital expenditures and is currently focusing on increasing production in New York. The company will not start construction in Germany until mid-2025 at the earliest, two years later than the original target.
The goal is no longer achievable
According to Reuters, in addition to the aforementioned companies, Infineon, STMicroelectronics, and GlobalFoundries have also announced plans to establish new factories in Europe after the EU introduced the Chip Act in 2022. The bill aims to raise 43 billion euros (47 billion US dollars) through public and private investment to strengthen the semiconductor industry in the region.
But two years have passed, and there are very few projects that have actually started construction, and even fewer projects that have received national assistance from the European Commission. Without approval, these projects are financially unfeasible. These delays have slowed down the region's efforts to achieve self-sufficiency and protect itself from the escalating trade tensions.
Jan Peter Kleinhans, a chip expert at the German technology and political think tank Interface (formerly known as Stiftung Neue Verantwortung), said that the EU's goal of winning a global market share of 20% by 2030 is no longer achievable. He added that given the interdependence of the chip market, self-sufficiency is not realistic.
However, "you have to be amazed by the number of projects that have already been released," Kleinhans said. "Even if a few of these projects will never be released."
Comparing the progress and issues of TSMC's Japanese and TSMC's American factories, TSMC's future progress in European factories is not only limited to subsidies. As mentioned earlier, the harsh working environment and overloaded working hours of wafer fabs are believed to be the main reasons for trapping European factories. Of course, the shortage of talent is also another factor that cannot be ignored.
