At the Shanghai International Symposium on Circuits and Systems held on May 25, He Tingbo, President of Huawei's Semiconductor Business Group, officially unveiled the Tao (τ) Law, a new principle guiding the development of the semiconductor industry, alongside a supporting academic paper.
Core Background: The Bottleneck of Moore's Law
For nearly 60 years, the global semiconductor industry evolved primarily driven by Moore's Law and Dennard Scaling. By shrinking transistor dimensions and advancing lithography processes, the industry continuously boosted transistor density and chip performance.
This development model gradually hit its limits starting in 2005. As transistors shrank further, chip leakage current and heat dissipation became increasingly severe. The widespread emergence of the "dark silicon" phenomenon meant most transistors could not operate efficiently simultaneously, resulting in a sharp drop in actual performance utilization.
When process nodes moved below 7nm, the industry faced more prominent bottlenecks. Performance gains from pure dimensional scaling diminished steadily. Signal latency in interconnects, rather than transistor performance, became the primary constraint on chip improvement. Meanwhile, R&D and manufacturing costs for advanced processes surged exponentially. Technological breakthroughs grew harder to achieve, and commercial cost-effectiveness kept declining. Moore's Law was trapped in dual predicaments of physical limitations and soaring economic costs.
Compounded by overseas tech restrictions, domestic semiconductor companies have been barred from accessing world-leading foundry services and advanced process technologies. The industry urgently needed to break away from the traditional nanometer scaling model, paving the way for the emergence of the Tao (τ) Law.
Core Tenets of the Tao (τ) Law
As the first fundamental evolutionary rule for the semiconductor industry proposed by a Chinese enterprise, the Tao (τ) Law abandons the nearly 60-year-old development logic centered on geometric scaling, as well as the simplistic evaluation standard that judges chip performance merely by process nanometer figures. Instead, it takes time scaling (τ) as its core evolutionary principle to replace geometric scaling, breaking the fixed iteration pattern of Moore's Law. Differentiated iteration coefficients are set for scenarios such as smartphones, autonomous driving and artificial intelligence to precisely match industrial demands and cut resource waste.
The law carries out layered optimizations across four tiers: components, circuits, chips and systems. Supported by the core technology of Logic Folding, it completely moves beyond traditional planar chip routing. Leveraging 3D stacking and hybrid bonding technologies, it restructures internal chip architectures, drastically shortening signal transmission paths vertically. This fundamentally addresses the high signal latency and limited performance growth of conventional planar chips.
- Component Layer: Optimize transistors, interconnect resistance and parasitic capacitance to minimize the device-level time constant τ at the physical foundation.
- Circuit Layer: Logic Folding breaks the physical boundaries of traditional planar layout, greatly shortening routing lengths on critical paths and reducing resistive and capacitive loads for signal propagation, thus delivering substantial improvements in transistor density and circuit performance.
- Chip Layer: Adopt full-stack collaborative design across software, architecture and chips. It enables fine-grained control over instruction and data flows based on real workloads, elevates system-level parallelism and efficiency, and significantly cuts end-to-end execution time.
- System Layer: Define the Lingqu Bus and revamp interconnection protocols for computing systems. It realizes unified memory addressing and native memory semantics across super nodes, substantially lowering system communication latency.
The technology has undergone six years of verification in mass production, with 381 chip models already rolled out commercially. The Kirin chip set to launch in autumn 2026 will be the first to adopt Logic Folding, followed by Huawei's Ascend AI chips. According to Huawei's roadmap, by 2031, the combination of the Tao (τ) Law and Logic Folding will enable high-end chips to reach the transistor density equivalent to the 1.4nm process.
Conclusion
From a long-term industrial perspective, the Tao Law represents one of the most practical and implementable technological evolution paths in the post-Moore era. Six years of mass production has fully proven the feasibility and stability of this technical system, offering a Chinese solution for the global semiconductor industry to break through existing bottlenecks.
Nevertheless, large-scale adoption and ecosystem maturation cannot be accomplished by a single enterprise. Going forward, the entire industrial chain — including semiconductor equipment, materials, design, manufacturing, packaging & testing, and software services — needs to pursue coordinated upgrading to jointly tackle common industry challenges such as technical adaptation, process optimization and standard formulation.
Moving ahead, with a maturing ecosystem and continuous technological iteration, the Tao Law will work in tandem with Moore's Law. It will help the global semiconductor industry step out of the race for shrinking process nodes and embrace a new phase of diversified, high-quality and cost-effective development, serving as a core driving force for domestic semiconductors to achieve leapfrog progress.
