Analysis of Silicon Carbide Technology Barriers: What are the Silicon Carbide Technology Barriers? What are the Silicon Carbide Technology Barriers
Silicon carbide chips are not only a new trend, but also a great challenge. So, let's analyze the technological barriers of silicon carbide. What are the technological barriers of silicon carbide? What are the technological barriers to silicon carbide?
1) The first generation of semiconductor materials, represented by traditional silicon (Si) and germanium (Ge), are the foundation of integrated circuit manufacturing and are widely used in low-voltage, low-frequency, low-power transistors and detectors. More than 90% of semiconductor products are made of silicon-based materials;
2) The second-generation semiconductor materials, represented by gallium arsenide (GaAs), indium phosphide (InP), and gallium phosphide (GaP), have high-frequency and high-speed optoelectronic properties compared to silicon-based devices, and are widely used in the fields of optoelectronics and microelectronics;
3) The third-generation semiconductor materials are represented by emerging materials such as silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), diamond (C), and aluminum nitride (AlN).
Silicon carbide is an important foundational material for the development of the third-generation semiconductor industry. Silicon carbide power devices, with their excellent high voltage resistance, high temperature resistance, and low loss performance, can effectively meet the high efficiency, miniaturization, and lightweight requirements of power electronic systems.
Due to its superior physical properties such as high bandgap (corresponding to high breakdown electric field and high power density), high conductivity, and high thermal conductivity, it is expected to become the most widely used basic material for semiconductor chip production in the future. Especially in the fields of new energy vehicles, photovoltaic power generation, rail transit, smart grids, etc., it has obvious advantages.
What are the technological barriers to silicon carbide? What are the technological barriers to silicon carbide?
The SiC production process is divided into three major steps: SiC single crystal growth, epitaxial layer growth, and device manufacturing, corresponding to the four major links of the industrial chain: substrate, epitaxy, and device and module.
The mainstream method of manufacturing substrates first uses the physical vapor sublimation method, which sublimates the powder in a high-temperature vacuum environment and grows silicon carbide crystals on the surface of the seed crystal through temperature field control. Using silicon carbide chips as substrates, a layer of single crystal is deposited on the chip using chemical vapor deposition to form epitaxial wafers. Among them, growing silicon carbide epitaxial layers on conductive silicon carbide substrates can produce successful devices, mainly used in fields such as electric vehicles and photovoltaics; Growing gallium nitride epitaxial layers on semi insulating silicon carbide substrates can further produce radio frequency devices, which are applied in fields such as 5G communication.
At present, the technical barrier and production difficulty of silicon carbide substrates are the highest in the silicon carbide industry chain.
The production bottleneck of SiC has not been completely resolved, and the unstable quality of raw material crystal columns leads to yield issues, which results in high costs for SiC devices.
On average, it only takes 3 days for silicon materials to grow into a crystal rod, but for silicon carbide crystal rods, it takes one week. A typical silicon crystal rod can grow up to 200 centimeters long, but a silicon carbide crystal rod can only grow up to 2 centimeters.
Moreover, SiC itself is a hard and brittle material, and wafers made from it are prone to edge breakage when using traditional mechanical cutting to cut wafers, which affects product yield and reliability.
SiC substrates are very different from traditional silicon ingots, and everything from equipment, processes, processing to cutting needs to be developed to process silicon carbide.
The silicon carbide industry chain is mainly divided into four links: substrate, epitaxial, device, and application. Substrate materials are the foundation of the industry chain, epitaxial materials are the key to device manufacturing, devices are the core of the industry chain, and applications are the driving force for industry development. Upstream industries use raw materials to produce substrate materials through methods such as physical vapor sublimation, and then use chemical vapor deposition to grow epitaxial materials. Midstream industries use upstream materials to produce RF devices, power devices, and other devices, which are ultimately applied to downstream 5G communication, electric vehicles, rail transit, etc. Among them, substrate and epitaxy account for 60% of the industry chain cost, which is the main value of the industry chain.
SiC substrate: SiC crystals are usually manufactured using the Lely method. International mainstream products are transitioning from 4 inches to 6 inches, and 8-inch conductive substrate products have been developed. Domestic substrates are mainly 4 inches. Due to the upgrade and transformation of the existing 6-inch silicon wafer production line for producing SiC devices, the high market share of 6-inch SiC substrates will be maintained for a long time.
The process of silicon carbide substrate is complex and difficult to produce. Silicon carbide substrate is a compound semiconductor single crystal material composed of two elements, carbon and silicon. At present, high-purity carbon powder and high-purity silicon powder are mainly used in the industry to synthesize silicon carbide powder. Under special temperature fields, mature physical vapor transmission (PVT) methods are used to grow silicon carbide ingots of different sizes in crystal growth furnaces. Finally, silicon carbide substrates are produced through multiple processes such as processing, cutting, grinding, polishing, and cleaning.
The technical difficulties of producing high-quality silicon carbide chips with stable mass production performance include:
1) Due to the need for crystals to grow in a high-temperature sealed environment above 2000 ℃, there is an extremely high requirement for temperature control;
2) Due to the existence of over 200 crystal structures in silicon carbide, only a few single crystal silicon carbide structures are the required semiconductor materials. During the crystal growth process, precise control of parameters such as silicon to carbon ratio, growth temperature gradient, crystal growth rate, and gas flow pressure is required;
3) The expansion technology for silicon carbide crystal growth under gas-phase transport method is extremely difficult;
4) The hardness of silicon carbide is close to that of diamond, making cutting, grinding, and polishing techniques difficult.
SiC epitaxy: It is usually manufactured by chemical vapor deposition (CVD) method, and is divided into n-type and p-type epitaxial wafers according to different doping types. Domestic Hantiancheng and Dongguan Tianyu are already able to provide 4-inch/6-inch SiC epitaxial wafers.
For SiC epitaxy, it is difficult to control in the high-voltage field, and the quality of SiC epitaxy has a significant impact on SiC devices. Moreover, the epitaxial equipment is monopolized by the four leading companies in the industry, Axitron, LPE, TEL, and Nuflare.
Silicon carbide epitaxial wafer refers to a silicon carbide wafer in which a single crystal thin film (epitaxial layer) with certain requirements and the same crystal as the substrate is grown on the original silicon carbide substrate. Epitaxial growth mainly uses CVD (Chemical Vapor Deposition) equipment or MBE (Molecular Beam Epitaxy) equipment. Due to the fact that silicon carbide devices are directly manufactured on the epitaxial layer, the quality of the epitaxial layer directly affects the performance and yield of the device. With the continuous improvement of the required voltage resistance performance of the device, the corresponding thickness of the epitaxial layer becomes thicker, and the difficulty of control becomes higher. When the general voltage is around 600V, the required thickness of the epitaxial layer is about 6 microns; When the voltage is between 1200-1700V, the required thickness of the epitaxial layer reaches 10-15 microns. If the voltage exceeds 10000 volts, an epitaxial layer thickness of over 100 microns may be required. As the thickness of the epitaxial layer continues to increase, it becomes increasingly difficult to control the uniformity of thickness, resistivity, and defect density.
SiC devices: Internationally, 600~1700V SiC SBDs and MOSFETs have been industrialized, with mainstream products having a voltage resistance level below 1200V and mainly packaged in TO packaging. In terms of price, the international price of SiC products is 5-6 times that of corresponding Si products, and is decreasing at a rate of 10% per year. With the expansion of upstream material devices and the increase in market supply in the next 2-3 years, prices will further decrease. It is expected that when the price reaches 2-3 times that of corresponding Si products, the advantages brought by the reduction of system costs and the improvement of performance will gradually drive SiC to occupy the market space of Si devices.
Traditional packaging is based on silicon-based materials, and third-generation semiconductor materials have a completely new design. If traditional silicon-based packaging structures are used for wide bandgap semiconductor power devices, it will bring new problems and challenges in terms of frequency, heat dissipation, and reliability. SiC power devices are more sensitive to parasitic capacitance and parasitic inductance. Compared to Si devices, SiC power chips have faster switching speeds, which can cause overshoot and oscillation in the waveform of the driving voltage, leading to increased switching losses and even causing power device misoperation in severe cases. In addition, SiC power devices have higher operating temperatures and higher requirements for heat dissipation.
Various structures have been developed in the field of wide bandgap semiconductor power packaging. Traditional Si based power module packaging is no longer applicable. In response to the problems of high parasitic parameters and poor heat dissipation efficiency in traditional Si based power module packaging, SiC power module packaging adopts wireless interconnection and double-sided cooling technologies in the structure, and selects substrate materials with better thermal conductivity. Various module packaging technologies have been developed by integrating decoupling capacitors, temperature/current sensors, and driver circuits into the module structure.
Moreover, there are high technological barriers and production costs in SiC device manufacturing.
Silicon carbide devices are formed by stacking epitaxial films on a silicon carbide substrate through CVD, followed by steps such as cleaning, oxidation, photolithography, etching, photoresist removal, ion implantation, chemical vapor deposition of silicon nitride, polishing, sputtering, and post-processing to form the device structure on a SiC single crystal substrate. Among them, SiC power devices mainly include SiC diodes, SiC transistors, and SiC power modules. Due to the slow production speed and low yield rate of upstream materials, silicon carbide devices have high manufacturing costs.
In addition, the manufacturing of silicon carbide devices has certain technical difficulties:
1) Specific processes that match the characteristics of silicon carbide materials need to be developed, such as: SiC has a high melting point that renders traditional thermal diffusion ineffective, requiring the use of ion implantation doping method and precise control of temperature, heating rate, duration, gas flow rate and other parameters; SiC is inert to chemical solvents, and dry etching and other methods should be used to optimize and develop mask materials, gas mixtures, control of sidewall slope, etching rate, sidewall roughness, etc;
2) The manufacturing of metal electrodes on silicon carbide chips requires a contact resistance of less than 10-5 Ω 2. The electrode materials Ni and Al that meet the requirements have poor thermal stability above 100 ℃, but the Al/Ni/W/Au composite electrode material with good thermal stability has a contact specific resistance 10-3 Ω 2 higher;
3) SiC has high cutting wear, and its hardness is second only to diamond, which puts higher demands on cutting, grinding, polishing and other technologies.
Moreover, groove type silicon carbide power devices have greater manufacturing difficulties. According to the different device structures, silicon carbide power devices can be mainly divided into planar devices and trench devices. Flat silicon carbide power devices have good unit consistency, simple manufacturing process, but are prone to JFET effect and have high parasitic capacitance and on state resistance. Compared to planar devices, groove type silicon carbide power devices have lower unit consistency and more complex manufacturing processes. However, the groove structure is beneficial for increasing device unit density, reducing the occurrence of JFET effect, and solving the problem of low channel mobility. It has excellent performance such as low on resistance, low parasitic capacitance, and low switching energy consumption, and has significant cost and performance advantages. It has become the mainstream direction of silicon carbide power device development. According to Rohm's official website, the ROHM Gen3 structure (Gen1 Trench structure) is only 75% of the area of the Gen2 (Plannar2) chip, and the on resistance of the ROHM Gen3 structure is reduced by 50% under the same chip size.
Silicon carbide substrate, epitaxy, front-end, research and development expenses, and others account for 47%, 23%, 19%, 6%, and 5% of the manufacturing cost of silicon carbide devices, respectively.
Finally, let's focus on breaking down the technical barriers of substrates in the silicon carbide industry chain.
The production process of silicon carbide substrate is similar to that of silicon-based substrate, but it is more difficult.
The production process of silicon carbide substrate generally includes raw material synthesis, crystal growth, ingot processing, crystal bar cutting, chip grinding, polishing, cleaning and other steps.
The crystal growth stage is the core of the entire process, which determines the electrical properties of the silicon carbide substrate.
Silicon carbide materials are difficult to grow in liquid phase under general conditions. Nowadays, the popular gas-phase growth method in the market has a growth temperature above 2300 ℃ and requires precise control of the growth temperature. The entire operation process is almost difficult to observe, and even a slight error can lead to product scrap.
In contrast, silicon materials only require 1600 ℃, which is much lower in demand.
The preparation of silicon carbide substrates still faces difficulties such as slow crystal growth rate and high crystal type requirements. Silicon carbide wafer growth takes about 7 to 10 days, while silicon rod pulling only takes 2 and a half days.
Moreover, silicon carbide is a material with a hardness second only to diamond, and a lot is lost during cutting, grinding, and polishing, with a yield ratio of only 60%.
We know that increasing the size of silicon carbide substrates is a trend, and as the size continues to grow, the requirements for diameter expansion technology are also increasing. Multiple technical control elements need to be integrated in order to achieve iterative diameter expansion growth of crystals.
According to data from Jibang Consulting, it is expected that by 2025, the global demand for 6-inch silicon carbide wafers in the electric vehicle market will be 1.69 million pieces. The market space is large, but there is still a lot of room for development in carbonization power technology, processes, production capacity, and other aspects.